| US 7,499,340 B2 | ||
| Semiconductor memory device and defect remedying method thereof | ||
| Kazuhiko Kajigaya, Iruma (Japan); Kazuyuki Miyazawa, Iruma (Japan); Manabu Tsunozaki, Ohme (Japan); Kazuyoshi Oshima, Ohme (Japan); Takashi Yamazaki, Ohme (Japan); Yuji Sakai, Machida (Japan); Jiro Sawada, Kokubunji (Japan); Yasunori Yamaguchi, Tokyo (Japan); Tetsurou Matsumoto, Higashiyamato (Japan); Shinji Udo, Akishima (Japan); Hiroshi Yoshioka, Akishima (Japan); Hirokazu Saito, Tokorozawa (Japan); Mitsuhiro Takano, Tokorozawa (Japan); Makoto Morino, Akishima (Japan); Sinichi Miyatake, Tokyo (Japan); Eiji Miyamoto, Ohme (Japan); Yasuhiro Kasama, Tokyo (Japan); Akira Endo, Hachioji (Japan); Ryoichi Hori, Tokyo (Japan); Jun Etoh, Hachioji (Japan); Masashi Horiguchi, Kawasaki (Japan); Shinichi Ikenaga, Koganei (Japan); and Atsushi Kumata, Kodaira (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan); and Hitachi VLSI Engineering Corp., Tokyo (Japan) | ||
| Filed on Jan. 09, 2008, as Appl. No. 12/7,336. | ||
| Application 08/159621 is a division of application No. 07/899572, filed on Jun. 18, 1992, abandoned. | ||
| Application 12/007336 is a continuation of application No. 11/714867, filed on Mar. 07, 2007, granted, now 7,345,929. | ||
| Application 11/714867 is a continuation of application No. 11/330220, filed on Jan. 12, 2006, granted, now 7,203,101. | ||
| Application 11/330220 is a continuation of application No. 11/101504, filed on Apr. 08, 2005, granted, now 7,016,236. | ||
| Application 11/101504 is a continuation of application No. 10/683260, filed on Oct. 14, 2003, granted, now 6,898,130. | ||
| Application 10/683260 is a continuation of application No. 10/254980, filed on Sep. 26, 2002, granted, now 6,657,901. | ||
| Application 10/254980 is a continuation of application No. 10/000032, filed on Dec. 04, 2001, granted, now 6,515,913. | ||
| Application 10/000032 is a continuation of application No. 09/714268, filed on Nov. 17, 2000, granted, now 6,335,884. | ||
| Application 09/714268 is a continuation of application No. 09/547917, filed on Apr. 11, 2000, granted, now 6,212,089. | ||
| Application 09/547917 is a continuation of application No. 09/361203, filed on Jul. 27, 1999, granted, now 6,160,744. | ||
| Application 09/361203 is a continuation of application No. 08/618381, filed on Mar. 19, 1996, granted, now 5,854,508. | ||
| Application 08/618381 is a continuation of application No. 08/455411, filed on May 31, 1995, granted, now 5,579,256. | ||
| Application 08/455411 is a continuation of application No. 08/159621, filed on Dec. 01, 1993, granted, now 5,602,771. | ||
| Application 07/899572 is a continuation of application No. 07/424904, filed on Oct. 18, 1989, abandoned. | ||
| Claims priority of application No. 63-277132 (JP), filed on Nov. 01, 1988; application No. 63-279239 (JP), filed on Nov. 07, 1988; application No. 1-14423 (JP), filed on Jan. 24, 1989; and application No. 1-65840 (JP), filed on Mar. 20, 1989. | ||
| Prior Publication US 2008/0205111 A1, Aug. 28, 2008 | ||
| Int. Cl. G11C 7/10 (2006.01) | ||
| U.S. Cl. 365—189.02 [365/230.03; 365/51; 365/63; 438/586; 438/587; 257/202; 257/203] | 18 Claims |
| 1. A semiconductor device formed in a rectangle region on a semiconductor substrate, said rectangle region comprising a first
region extending along a first center line which intersects a middle point of a first side of said rectangle region, wherein
said first region divides said rectangle region to form a second region and a third region, said semiconductor device comprising:
a first memory array comprising a plurality of first dynamic memory cells of N bits, the first memory array being formed in
said second region;
a second memory array comprising a plurality of second dynamic memory cells of N bits, the second memory array being formed
in said third region;
a plurality of bonding pads formed in said first region; and
a voltage generating circuit for receiving a first voltage and for generating a second voltage which is different from said
first voltage, said voltage generating circuit being formed in said first region,
wherein the first memory array further includes:
a plurality of word lines coupled to the plurality of first and second dynamic memory cells;
a plurality of bit lines coupled to the plurality of first and second dynamic memory cells; and
a plurality of sense amplifiers connected to said plurality of bit lines,
wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the
number of column address bits,
wherein the number of activated sense amplifiers per one memory access is expressed as n/2x,
wherein said N bits obtained through said activated sense amplifiers are output as data, and
wherein said N is one of numbers in a progression expressed as 2k, k=2, 3, 4, - - - .
|