| US 7,498,860 B2 | ||
| Buffer circuit having multiplexed voltage level translation | ||
| Dipankar Bhattacharya, Macungie, Pa. (US); Carol A. Huber, Macungie, Pa. (US); Makeshwar Kothandaraman, Whitehall, Pa. (US); John C. Kriz, Palmerton, Pa. (US); and Bernard L. Morris, Emmaus, Pa. (US) | ||
| Assigned to Agere Systems Inc., Allentown, Pa. (US) | ||
| Filed on Mar. 27, 2007, as Appl. No. 11/691,590. | ||
| Prior Publication US 2008/0238399 A1, Oct. 02, 2008 | ||
| Int. Cl. H03L 5/00 (2006.01) | ||
| U.S. Cl. 327—333 [327/407] | 18 Claims |
| 1. A buffer circuit selectively operative in one of at least a first mode and a second mode as a function of a first control
signal supplied to the buffer circuit, the buffer circuit comprising:
interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and
to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage
level, the output signal being a function of the second control signal in the first mode and being a function of the third
control signal in the second mode; and
first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including
at least one control input operative to receive the output signal generated by the interface circuitry;
wherein the interface circuitry comprises at least one voltage level translator circuit operative to receive, as a function
of the first control signal, one of at least the second and third control signals, and to generate the output signal, the
output signal of the voltage level translator circuit having a value indicative of the second control signal in the first
mode of operation and having a value indicative of the third control signal in the second mode of operation.
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