| US 7,498,852 B1 | ||
| Phase error correction circuit for a high speed frequency synthesizer | ||
| Sandeep Agarwal, Fremont, Calif. (US); and Xiaole Chen, San Jose, Calif. (US) | ||
| Assigned to Intersil Americas Inc., Milpitas, Calif. (US) | ||
| Filed on Mar. 15, 2007, as Appl. No. 11/686,356. | ||
| Application 11/686356 is a continuation of application No. 11/045929, filed on Jan. 28, 2005, granted, now 7,205,798. | ||
| Claims priority of provisional application 60/575667, filed on May 28, 2004. | ||
| Int. Cl. H03B 21/00 (2006.01) | ||
| U.S. Cl. 327—105 [327/106; 327/107; 708/101; 708/271; 708/276] | 20 Claims |
| 1. A method of adjusting a frequency of a pixel clock comprising:
receiving a first signal;
generating the pixel clock;
dividing the pixel clock;
comparing a phase of the first signal to a phase of the divided pixel clock to generate a phase error signal;
accumulating the phase error signal to generate an overflow and a remainder signal;
generating a plurality of clock signals, each separated in phase;
retiming the overflow signal to the plurality of clock signals to generate a plurality of retimed overflow signals; and
selecting one of the plurality of retimed overflow signals using one or more bits of the remainder signal.
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