| US 7,498,630 B2 | ||
| Nonvolatile semiconductor memory | ||
| Masayuki Ichige, Yokohama (Japan); Koji Hashimoto, Yokohama (Japan); Tatsuaki Kuji, Fukaya (Japan); Seiichi Mori, Ota-ku (Japan); Riichiro Shirota, Fujisawa (Japan); Yuji Takeuchi, Yokohama (Japan); and Koji Sakui, Setagaya-ku (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Nov. 14, 2006, as Appl. No. 11/559,785. | ||
| Application 11/008531 is a division of application No. 10/359216, filed on Feb. 06, 2003, granted, now 6,845,042. | ||
| Application 11/559785 is a continuation of application No. 11/008531, filed on Dec. 10, 2004, granted, now 7,141,474. | ||
| Claims priority of application No. 2003-028413 (JP), filed on Feb. 05, 2003. | ||
| Prior Publication US 2007/0070708 A1, Mar. 29, 2007 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—314 [257/316; 257/319; 257/E21.069; 257/E21.103; 438/258; 438/593; 365/185.17] | 20 Claims |
| 1. A nonvolatile semiconductor memory embedded in a card operable so as to receive and transfer a predetermined signal from
an external device, and the nonvolatile semiconductor memory comprising:
a plurality of word lines disposed in a row direction;
a plurality of bit lines disposed in a column direction perpendicular to the word lines;
memory cell transistors having a source region, a drain region, a gate electrode and a charge storage layer, provided in the
column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the
plurality of the word lines connected to the memory cell;
a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in
the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory
cell transistors; and
a first select gate line connected to each of the gate electrodes of the first select transistors, wherein
the plurality of the word lines have a wiring line width which is the same as the first select gate line.
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