| US 7,498,619 B2 | ||
| Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process | ||
| Mario G. Saggio, Acicastello (Italy); and Ferruccio Frisina, Sant' Agata Li Battiati (Italy) | ||
| Assigned to STMicroelectronics S.r.l., Agrate Brianza (Italy) | ||
| Filed on Feb. 23, 2006, as Appl. No. 11/362,435. | ||
| Claims priority of application No. 05425102 (EP), filed on Feb. 25, 2005. | ||
| Prior Publication US 2006/0194391 A1, Aug. 31, 2006 | ||
| Int. Cl. H01L 21/332 (2006.01) | ||
| U.S. Cl. 257—197 [257/328; 257/273; 257/341; 257/E21.417; 257/E29.256; 257/E21.383; 438/138; 438/135] | 11 Claims |
| 1. A power electronic device of the multi-drain type integrated on a semiconductor substrate of a first type of conductivity
comprising a plurality of elemental units, each elemental unit comprising:
a body region of a second type of conductivity realized on a first semiconductor layer of the first type of conductivity formed
on said semiconductor substrate,
a column region of the second type of conductivity realized in an underlying second semiconductor layer below said body region,
wherein said second semiconductor layer comprises at least three sub-semiconductor layers, overlapped on each other, wherein
the resistivity of each sub-semiconductor layer is different from that of the other sub-semiconductor layers and said resistivity
decreases in each sub-semiconductor layer upwards towards the first semiconductor layer, and
wherein said column region comprises at least three doped sub-regions, each one realized in one of said sub-semiconductor
layers, wherein the amount of charge of each doped sub-region balances the amount of charge of the sub-semiconductor layer
in which each doped sub-region is realized and doping concentration increases in each doped sub-region upwards towards the
first semiconductor layer.
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