US 7,498,520 B2
Semiconductor multilayer wiring board and method of forming the same
Tetsuya Osaka, Tokyo (Japan); Tokihiko Yokoshima, Tokyo (Japan); Isao Sato, Kawasaki (Japan); Akira Hashimoto, Kawasaki (Japan); and Yoshio Hagiwara, Kawasaki (Japan)
Assigned to Waseda University, Tokyo (Japan); and Tokyo Ohka Kogyo Co., Ltd., Kanagawa Prefecture (Japan)
Filed on Oct. 18, 2004, as Appl. No. 10/965,868.
Claims priority of application No. 2003-358433 (JP), filed on Oct. 17, 2003; and application No. 2004-265445 (JP), filed on Sep. 13, 2004.
Prior Publication US 2005/0110149 A1, May 26, 2005
Int. Cl. H05K 3/02 (2006.01); H05K 1/00 (2006.01)
U.S. Cl. 174—250  [29/846] 9 Claims
OG exemplary drawing
 
1. A semiconductor multilayer wiring board having a semiconductor multilayer wiring, said semiconductor multilayer wiring board comprising:
a lower wiring layer formed on a semiconductor substrate;
a silica-based interlayer insulating layer having a low dielectric constant and made of a spin-on-glass (SOG) material, said silica-based interlayer insulating layer having a wiring-layer-forming space formed therein by a dual damascene process;
a silane-based monomolecular layer film on an inner surface of said wiring-layer-forming space in said silica-based interlayer insulating layer;
a plated film on a surface of said monomolecular layer film;
an upper wiring layer formed on said lower wiring layer via said silica-based interlayer insulating layer; and
a copper wiring layer on said plated film such that said lower wiring layer and said upper wiring layer are connected to each other by said copper wiring layer vertically penetrating through said silica-based interlayer insulating layer.