| US 7,498,217 B2 | ||
| Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers | ||
| Jung-Min Oh, Incheon (Korea, Republic of); Jeong-Nam Han, Seoul (Korea, Republic of); Chang-Ki Hong, Seongnam-si (Korea, Republic of); Kun-Tack Lee, Suwon-si (Korea, Republic of); Dae-Hyuk Kang, Hwaseong-si (Korea, Republic of); Woo-Gwan Shim, Yongin-si (Korea, Republic of); and Jong-Won Lee, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on May 10, 2007, as Appl. No. 11/746,761. | ||
| Claims priority of application No. 10-2006-0043035 (KR), filed on May 12, 2006. | ||
| Prior Publication US 2007/0264793 A1, Nov. 15, 2007 | ||
| Int. Cl. H01L 21/8238 (2006.01); H01L 21/8242 (2006.01); H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—201 [438/211; 438/248; 438/257; 438/263; 438/593; 257/E21.209; 257/E21.21; 257/E21.422; 257/E21.423; 257/E21.679] | 26 Claims |
| 1. A method of manufacturing a semiconductor device, the method comprising:
forming a trench in a substrate;
forming an isolation layer in the trench such that the isolation layer protrudes from the substrate;
forming a first layer on the substrate exposed by the isolation layer;
forming a preliminary second layer pattern on the first layer, wherein an upper face of the preliminary second layer pattern
is at a level above the substrate that is substantially lower than, or substantially equal to, a level above the substrate
of an upper face of the isolation layer;
forming a third layer on the preliminary second layer and the isolation layer;
forming a fourth layer on the third layer;
partially etching the fourth layer, the third layer, the preliminary second layer pattern and the first layer to form a gate
structure on the substrate, wherein the gate structure comprises a first layer pattern, a second layer pattern, a third layer
pattern and a fourth layer pattern; and
forming source/drain regions at portions of the substrate adjacent to the gate structure.
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