| US 7,498,194 B2 | ||
| Semiconductor arrangement | ||
| Nikolaus Bott, Villach (Austria); Oliver Haeberlen, Villach (Austria); Manfred Kotek, Villach (Austria); Joost Larik, Villach (Austria); Josef Maerz, Munich (Germany); and Ralf Otremba, Kaufbeuren (Germany) | ||
| Assigned to Infineon Technologies AG, Munich (Germany) | ||
| Filed on Apr. 11, 2007, as Appl. No. 11/733,930. | ||
| Application 11/733930 is a division of application No. 10/850157, filed on May 20, 2004, granted, now 7,233,059. | ||
| Claims priority of application No. 103 23 007 (DE), filed on May 21, 2003. | ||
| Prior Publication US 2007/0178624 A1, Aug. 02, 2007 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—106 [438/637] | 15 Claims |
| 1. A method for fabricating a semiconductor arrangement comprising:
providing a lower semiconductor component with a topmost, patterned metallization;
depositing a passivation layer;
patterning the passivation layer by means of photolithography and a first etching step;
depositing a polyimide layer;
opening the polyimide layer in a contact pad region by means of photolithography;
fixing an upper semiconductor component on the passivation layer; and
sheathing the semiconductor arrangement with a molding composition, wherein after patterning, the passivation layer essentially
remains only in the region below the upper semiconductor component.
|