a master circuit for generating an internal signal having the same cycle or the same phase as that of an input reference signal on the basis of a control signal generated by feedback control, said master circuit comprising a comparator circuit for comparing the cycle or phase of said internal signal with that of said reference signal, a control signal generating circuit for varying said control signal in accordance with an output of said comparator circuit, and a first variable delay line for outputting said internal signal by controlling a delay amount for said reference signal in accordance with said control signal, said control signal generating circuit including a charge pump circuit for controlling an output voltage level in accordance with an up signal and a down signal from said comparator circuit;

at least two slave circuits each for generating a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and said control signal from said master circuit, each of said at least two slave circuits comprising a second variable delay line for outputting said timing signal by delaying said internal signal, and a phase interpolator for accepting input signals of different phases and for outputting a finer timing signal of an intermediate phase, without comprising a comparator circuit for comparing the cycle or phase of said internal signal with that of said reference signal, and a control signal generating circuit for varying said control signal in accordance with an output of said comparator circuit; and

at least two receiver circuits, each receiving the finer timing signal output from corresponding one of said slave circuits, latching a receiving signal and detecting a level of the receiving signal based on the finer timing signal, and feedback controlling a delay value of the input signals to said phase interpolator.