| US 7,496,709 B2 | ||
| Integrated circuit memory device having delayed write timing based on read response time | ||
| Richard M. Barth, Palo Alto, Calif. (US); Frederick A. Ware, Los Altos Hills, Calif. (US); Donald C. Stark, Los Altos, Calif. (US); Craig E. Hampel, San Jose, Calif. (US); Paul G. Davis, San Jose, Calif. (US); Abhijit M. Abhyankar, Sunnyvale, Calif. (US); James A. Gasbarro, Mountain View, Calif. (US); and David Nguyen, San Jose, Calif. (US) | ||
| Assigned to Rambus Inc., Los Altos, Calif. (US) | ||
| Filed on Dec. 10, 2007, as Appl. No. 11/953,803. | ||
| Application 10/128167 is a division of application No. 09/169206, filed on Oct. 09, 1998, granted, now 6,401,167. | ||
| Application 11/953803 is a continuation of application No. 11/692159, filed on Mar. 27, 2007, granted, now 7,330,952. | ||
| Application 11/692159 is a continuation of application No. 11/059216, filed on Feb. 15, 2005, granted, now 7,197,611. | ||
| Application 11/059216 is a continuation of application No. 10/128167, filed on Apr. 22, 2002, granted, now 6,868,474. | ||
| Claims priority of provisional application 60/061770, filed on Oct. 10, 1997. | ||
| Prior Publication US 2008/0091907 A1, Apr. 17, 2008 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—105 [711/167] | 50 Claims |
| 1. A semiconductor memory device comprising:
a memory core to store data;
a first set of interconnect resources to receive write data; and
a second set of interconnect resources to receive:
a write command associated with the write data; and
information indicating whether mask information is included with the write command, wherein the mask information specifies
whether to selectively write portions of the write data to the memory core.
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