US 7,496,706 B2
Message signaled interrupt redirection table
Tom L. Nguyen, Auburn, Wash. (US); and Steven R. Carbonari, Beaverton, Oreg. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Jun. 30, 2004, as Appl. No. 10/882,922.
Prior Publication US 2006/0015668 A1, Jan. 19, 2006
Int. Cl. G06F 13/24 (2006.01); G06F 13/32 (2006.01)
U.S. Cl. 710—269 13 Claims
OG exemplary drawing
 
1. A chip comprising:
interface circuitry to provide received untranslated message signal interrupt (MSI) signals and translated MSI signals, wherein the MSI includes a data value;
a MSI redirection table (MRT) that includes entries having an address field and a data field;
wherein the data field of the received untranslated MSI signal includes a physical interrupt vector, which is an index into a local advanced programmable interrupt controller interrupt description table;
redirection circuitry to receive MSI signals each having an address field, a data field, and a redirection field, and wherein if the redirection field for particular ones of the MSI signals has a first value, the redirection circuitry passes those MSI signals to the interface circuitry as the untranslated MSI signals and if the redirection field for particular ones of the MSI signals has a second value, the redirection circuitry passes those MSI signals to translation circuitry, wherein the MSI signal translation circuitry includes:
matching circuitry to identify entries in the MRT based on at least part of the data field of the MSI signals to be translated, wherein the at least part of the data field acts as an index to the MRT; and
copying circuitry to create the translated MSI signals by copying at least a portion of data and address contents of valid identified entries into at least a portion of the address and data fields of the MSI signals to be translated, and to provide the translated MSI signals to the interface circuitry.