| US 7,495,993 B2 | ||
| Onboard data storage and method | ||
| Kang-Huai Wang, Saratoga, Calif. (US) | ||
| Assigned to Capso Vision, Inc., Saratoga, Calif. (US) | ||
| Filed on Oct. 25, 2006, as Appl. No. 11/552,880. | ||
| Claims priority of provisional application 60/760794, filed on Jan. 19, 2006. | ||
| Claims priority of provisional application 60/760079, filed on Jan. 18, 2006. | ||
| Claims priority of provisional application 60/739162, filed on Nov. 23, 2005. | ||
| Claims priority of provisional application 60/730797, filed on Oct. 26, 2005. | ||
| Prior Publication US 2007/0091713 A1, Apr. 26, 2007 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.09 [365/233.1; 365/236; 365/239; 365/240] | 38 Claims |
| 1. A semiconductor memory device, comprising:
a memory array comprising a plurality of memory cells, each memory cell being addressed by selectively activating one of a
plurality word lines and one of a plurality of bit lines;
an input for receiving a clock signal;
a counter for providing successively a plurality of addresses according to a predetermined sequence in response to the clock
signal;
a first address circuit that receives the addresses and activates word lines corresponding to the addresses;
a second address circuit that activates bit lines; and
a register provided between the output terminals of the counter and the first address circuit, the register providing each
of the addresses to the first address circuit after a predetermined delay from the clock signal.
|