| US 7,495,948 B2 | ||
| Semiconductor memory | ||
| Toshikazu Suzuki, Hyogo (Japan); Yoshinobu Yamagami, Kyoto (Japan); and Satoshi Ishikura, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Dec. 13, 2006, as Appl. No. 11/637,691. | ||
| Claims priority of application No. 2005-365102 (JP), filed on Dec. 19, 2005; and application No. 2006-151542 (JP), filed on May 31, 2006. | ||
| Prior Publication US 2007/0139997 A1, Jun. 21, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—154 [365/185.05; 365/185.07; 365/189.04; 365/230.05] | 33 Claims |
| 1. A semiconductor memory, comprising:
word lines and bit lines arranged in a matrix;
a plurality of memory cells provided at intersections of the word lines and the bit lines; and
a low-data holding power supply control circuit for controlling a potential of a low-data holding power supply coupled to
memory cells provided on a corresponding one of the bit lines,
wherein each of the plurality of memory cells has two cross-coupled inverter circuits for holding a pair of high data and
low data, and
the low-data holding power supply control circuit controls, in a write operation, a potential of a low-data holding power
supply of a memory cell corresponding to a selected bit line to be higher than a potential of a low-data holding power supply
of a memory cell corresponding to an unselected bit line.
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