US 7,495,928 B2
Semiconductor device and printed circuit board
Tohru Ohsaka, Yokohama (Japan)
Assigned to Canon Kabushiki Kaisha, Tokyo (Japan)
Filed on Dec. 19, 2007, as Appl. No. 11/960,161.
Application 11/960161 is a division of application No. 11/094136, filed on Mar. 31, 2005, granted, now 7,349,224.
Claims priority of application No. 2004-121434 (JP), filed on Apr. 16, 2004; and application No. 2005-045617 (JP), filed on Feb. 22, 2005.
Prior Publication US 2008/0128873 A1, Jun. 05, 2008
Int. Cl. H05K 7/10 (2006.01); H05K 7/12 (2006.01)
U.S. Cl. 361—767  [361/770; 361/774] 1 Claim
OG exemplary drawing
 
1. A semiconductor circuit assembly, comprising:
a motherboard; and
a semiconductor device mounted on the motherboard,
wherein the semiconductor device includes a semiconductor element and an interposer substrate on which the semiconductor substrate is mounted, a first electrode pad is connected to the semiconductor element by a first signal line and is also connected, by a via, to a pad provided on the reverse face of the interposer substrate, a second electrode pad is connected to the first electrode pad by a second signal line and is located nearer an outer edge of the interposer substrate than the first electrode pad that is connected to the pad on the reverse face of the interposer substrate, and a third signal line extends from the second electrode pad to the outer edge of the interposer substrate,
wherein the first and second electrode pads and the third signal line are formed on an obverse surface of the interposer substrate,
wherein the first electrode pad is connected to a fourth signal line, on the motherboard, through a via and the pad arranged on the reverse face of the interposer substrate, and the second electrode pad is connected to a fifth signal line, on the motherboard, through a via and the pad arranged on the reverse face of the interposer substrate and is also terminated by a terminating resistor, and
wherein each of the first, second, and third signal lines is a differential pair of signal lines, for each of which two signal lines are arranged in parallel at a predetermined interval.