| US 7,495,281 B2 | ||
| Non-volatile memory device and methods of forming and operating the same | ||
| Seung-Jin Yang, Seoul (Korea, Republic of); Jeong-Uk Han, Suwon-si (Korea, Republic of); Kwang-Wook Koh, Seoul (Korea, Republic of); Jae-Hwang Kim, Yongin-si (Korea, Republic of); Sung-Chul Park, Gwacheon-si (Korea, Republic of); and Ju-Ri Kim, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jul. 19, 2006, as Appl. No. 11/488,983. | ||
| Claims priority of application No. 10-2005-0069564 (KR), filed on Jul. 29, 2005. | ||
| Prior Publication US 2007/0023820 A1, Feb. 01, 2007 | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—315 [257/316; 257/319; 257/E29.304] | 10 Claims |
| 1. A non-volatile memory device comprising a plurality of memory cell transistors, wherein each of the memory cell transistors
comprises:
a first gate insulation layer on a semiconductor substrate;
a floating gate on the first gate insulation layer;
a second gate insulation layer covering a top and sidewalls of the floating gate;
a first sidewall selection gate on the second gate insulation layer at a first sidewall of the floating gate;
a second sidewall selection gate on the second gate insulation layer at a second sidewall of the floating gate;
an inter-gate dielectric layer on the first sidewall selection gate, the second gate insulation layer and the second sidewall
selection gate;
a control gate overlapping the floating gate on the inter-gate dielectric layer;
a source region in the semiconductor substrate adjacent the first sidewall selection gate and spaced apart from the floating
gate; and
a drain region in the semiconductor substrate adjacent the second sidewall selection gate and spaced apart from the floating
gate.
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