| US 7,495,278 B2 | ||
| Non-volatile memory and semiconductor device | ||
| Shunpei Yamazaki, Tokyo (Japan); and Jun Koyama, Kanagawa (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., (Japan) | ||
| Filed on May 16, 2005, as Appl. No. 11/129,795. | ||
| Application 11/129795 is a continuation of application No. 10/424575, filed on Apr. 28, 2003, granted, now 6,900,499. | ||
| Application 10/424575 is a continuation of application No. 09/970719, filed on Oct. 04, 2001, granted, now 6,597,034, filed on Jul. 22, 2003. | ||
| Application 09/970719 is a continuation of application No. 09/138691, filed on Aug. 24, 1998, granted, now 6,323,515, filed on Nov. 27, 2001. | ||
| Claims priority of application No. 9-249818 (JP), filed on Aug. 29, 1997; application No. 10-132750 (JP), filed on Apr. 27, 1998; and application No. 10-161365 (JP), filed on May 25, 1998. | ||
| Prior Publication US 2005/0218405 A1, Oct. 06, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/72 (2006.01) | ||
| U.S. Cl. 257—314 [257/316; 257/347; 257/350; 257/52; 257/83; 257/88] | 24 Claims |
| 1. A cellular phone having a non-volatile memory, the non-volatile memory comprising:
a first thin film transistor and a second thin transistor formed over a substrate,
wherein the first thin film transistor comprises:
a first semiconductor layer having first source and drain regions and a first channel region interposed therebetween;
a gate electrode formed over the first channel region with a first gate insulating film interposed therebetween; and
a second insulating film formed over the gate electrode,
wherein the second thin film transistor comprises:
a second semiconductor layer having second source and drain regions and a second channel region interposed therebetween;
a floating gate electrode formed over the second channel region with a second gate insulating film interposed therebetween;
a third insulating film formed over the floating gate electrode; and
a control gate electrode formed over the third insulating film,
wherein an interlayer insulating film is formed over and in contact with the second insulating film and the control gate electrode,
and
wherein the substrate is an insulating substrate.
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