| US 7,494,923 B2 | ||
| Manufacturing method of wiring substrate and semiconductor device | ||
| Hiroko Yamamoto, Kanagawa (Japan); and Osamu Nakamura, Kanagawa (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., (Japan) | ||
| Filed on Jun. 13, 2005, as Appl. No. 11/151,003. | ||
| Claims priority of application No. 2004-175833 (JP), filed on Jun. 14, 2004. | ||
| Prior Publication US 2005/0276912 A1, Dec. 15, 2005 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—662 [438/660; 438/669; 438/676; 257/E21.533; 257/E21.534; 257/E21.535; 257/E21.582] | 27 Claims |
| 1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a pattern by discharging a composition comprising metal particles and an organic resin over a substrate by a droplet
discharging method;
irradiating a portion of the pattern with laser light to bake a portion of the metal particles included in the pattern to
form a wiring wherein a remaining portion of the pattern not irradiated with the laser light remains adjacent to side surfaces
of the wiring, and
forming an insulating layer over the wiring and the remaining portion.
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