forming a plurality of first gate structures in a cell area of a semiconductor substrate, and other gate structures in a peripheral circuit area of the semiconductor substrate;

forming contact regions in an upper portion of the cell area of the semiconductor substrate between adjacent ones of the first gate structures;

forming a protection layer on the cell area and peripheral circuit area of the semiconductor substrate to directly contact the first gate structures and other gate structures and the contact regions;

forming an insulation structure on the protection layer; and,

forming a plurality of contacts, including a first plurality of contacts respectively extending through the insulation structure and the protection layer to directly contact one of the contact regions and one of the first gate structures in the cell area, and a second plurality of contacts respectively extending through the insulation structure and the protection layer to directly contact either one of the other gate structures or a portion of the semiconductor substrate in the peripheral circuit area, wherein the plurality of contacts includes contacts having substantially different heights,

wherein forming the plurality of contacts comprises:

forming a plurality of contact holes extending through the insulation structure to expose portions of the protection layer;

etching the exposed portions of the protection layer to expose respectively, the one contact region and sidewalls of the first gate structures in the cell area, the portion of the semiconductor substrate in the peripheral circuit area, and one of the other gate structures; and

filling the plurality of contact holes with a conductive material.