| US 7,334,205 B1 | ||
| Optimization of die placement on wafers | ||
| Eitan Cadouri, Cupertino, Calif. (US) | ||
| Assigned to PDF Solutions, Inc., San Jose, Calif. (US) | ||
| Filed on Nov. 22, 2004, as Appl. No. 10/995,903. | ||
| Application 10/995903 is a continuation of application No. 10/428747, filed on May 02, 2003, granted, now 6,826,738. | ||
| Claims priority of provisional application 60/379194, filed on May 10, 2002. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 17/50 (2006.01); G06F 19/00 (2006.01) | ||
| U.S. Cl. 716—9 [716/10; 716/2; 700/97; 700/103; 700/121] | 20 Claims |
| 1. A method of optimizing layout of semiconductor devices on a wafer, comprising:
obtaining at least one effect on at least one aspect of production of the semiconductor devices on the after due to at least
one manufacturing component, wherein at least one manufacturing component is a process or machine used in the production of
the semiconductor devices on the wafer;
obtaining user input data corresponding to at least one optimization target; and
performing an optimization based on the at least one effect and the user input data to determine a layout of the semiconductor
devices on the wafer, wherein performing the optimization includes analyzing different patterns for placing the semiconductor
devices on the wafer.
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