| US 7,334,202 B1 | ||
| Optimizing critical dimension uniformity utilizing a resist bake plate simulator | ||
| Bhanwar Singh, Morgan Hill, Calif. (US); Qiaolin Zhang, Albany, Calif. (US); Iraj Emami, Austin, Tex. (US); Joyce S. Oey Hewett, Austin, Tex. (US); and Luigi Capodiece, Santa Cruz, Calif. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Jun. 03, 2005, as Appl. No. 11/145,327. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—4 | 25 Claims |
| 1. A system for optimizing critical dimension uniformity in semiconductor manufacturing processes, comprising:
a bake plate simulator that includes a thermal model of a bake plate;
a finite element analysis engine that accesses data from the thermal model and calculates a heat diffusion equation wherein
the heat diffusion equation differentiates temperature with respect to at least two spatial coordinates of a zone; and
a lithography simulator that uses calculation results from the finite element analysis engine to derive predicted results
of a lithographic process.
|