| US 7,334,159 B1 | ||
| Self-testing RAM system and method | ||
| David M. Callaghan, Concord, Ohio (US) | ||
| Assigned to Rockwell Automation Technologies, Inc., Mayfield Heights, Ohio (US) | ||
| Filed on Sep. 29, 2003, as Appl. No. 10/674,044. | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—30 [714/5; 714/6; 714/8; 714/42; 365/200] | 39 Claims |
| 1. A self-testing random access memory (RAM) system for a computer, comprising:
a memory array;
a self-testing RAM interface that includes a microprocessor, the self-testing RAM interface is embedded on a circuit board
with the memory array and tests integrity of data stored in the memory array;
the self-testing RAM interface with the memory array and a central processing unit (CPU) of the computer are formed on separate
integrated circuits and the self-testing RAM interface cooperates with the CPU to facilitate testing memory array data cells
by dividing the memory array, so that each of the CPU and the microprocessor concurrently test the array thus facilitating
faster testing of the memory array.
|