| US 7,333,362 B2 | ||
| Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane | ||
| Philippe Gendrier, Grenoble (France); Cyrille Dray, Eybens (France); Richard Fournel, Lumbin (France); Sébastien Poirier, Vizille (France); Daniel Caspar, Saint Hilaire du Touvet (France); and Philippe Candelier, Saint Mury Monteymond (France) | ||
| Assigned to STMicroelectronics SA, Montrouge (France) | ||
| Appl. No. 10/511,712 PCT Filed Jan. 31, 2003, PCT No. PCT/FR03/00311 § 371(c)(1), (2), (4) Date Apr. 18, 2005, PCT Pub. No. WO03/088366, PCT Pub. Date Oct. 23, 2003. |
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| Claims priority of application No. 02 04690 (FR), filed on Apr. 15, 2002; and application No. 02 09454 (FR), filed on Jul. 25, 2002. | ||
| Prior Publication US 2005/0219912 A1, Oct. 06, 2005 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.01 [365/185.26; 365/185.02; 365/185.33] | 67 Claims |
| 1. A semiconductor memory device comprising:
at least one electrically erasable and programmable non-volatile memory cell including
a layer of gate material,
a floating-gate transistor including a floating gate defined in the layer of gate material, and further including source,
drain and channel regions defining a control gate,
a first active zone, and
a second active zone incorporating the control gate and electrically isolated from the first active zone,
a dielectric zone between a first part of the layer of gate material and the first active zone;
the dielectric zone defining a transfer zone for transferring, during erasure of the memory cell, charges stored in the floating
gate to the first active zone.
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