| US 7,493,574 B2 | ||
| Method and system for improving yield of an integrated circuit | ||
| Hongzhou Liu, Pittsburgh, Pa. (US); and Rodney M. Phelps, Pittsburgh, Pa. (US) | ||
| Assigned to Cadence Designs Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Feb. 23, 2006, as Appl. No. 11/361,928. | ||
| Prior Publication US 2007/0198956 A1, Aug. 23, 2007 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—1 [716/2; 716/4] | 27 Claims |
| 1. A method for improving yield of an integrated circuit, comprising:
optimizing a design of the integrated circuit according to a set of predefined design parameters to generate design points
that meet a set of predefined design specifications;
analyzing the design points to form clusters comprising the design points;
determining a representative design point from the clusters comprising the design points;
running a statistical simulation to determine a yield of the design using the representative design point and a statistical
model of manufacturing process variations;
generating statistical corners in accordance with results of the statistical simulation; and
optimizing the design in accordance with the statistical corners using an iterative process.
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