| US 7,493,476 B2 | ||
| Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence | ||
| Gerard Chauvel, Antibes (France); Jean-Philippe Lesot, Etrelles (France); and Gilbert Cabillic, Brece (France) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Jul. 25, 2005, as Appl. No. 11/188,827. | ||
| Claims priority of application No. 04291918 (EP), filed on Jul. 27, 2004. | ||
| Prior Publication US 2006/0026391 A1, Feb. 02, 2006 | ||
| Int. Cl. G06F 9/22 (2006.01) | ||
| U.S. Cl. 712—220 | 16 Claims |
| 1. A processor, comprising:
decode logic coupled to an instruction cache;
a micro-sequence vector table coupled to the decode logic, wherein the micro-sequence vector table comprises an entry for
each bytecode in an instruction set of the processor; and
a register coupled to said decode logic, wherein the register is dedicated for storage of an immediate operand of a bytecode,
wherein the decode logic is configured to:
obtain a single bytecode from the instruction cache, wherein the single bytecode requires an immediate operand stored in the
instruction cache,
use the single bytecode to locate an entry corresponding to the single bytecode in the micro-sequence vector table, wherein
a size of the immediate operand is indicated by bits in the entry, and
when indicated by information in the entry, obtain the immediate operand from the instruction cache and store the immediate
operand in the register for use by a micro-sequence that is executed in lieu of the single bytecode,
wherein the information in the entry comprises an indicator set to indicate that the micro-sequence is to be executed in lieu
of the single bytecode and an indicator set to indicate that the immediate operand is to be obtained.
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