receiving a supply voltage, a PMOS back bias voltage, and an NMOS back bias voltage;

receiving a clock signal;

propagating the clock signal through a timing comparison circuit;

measuring a delay in the propagation of the clock signal through the timing comparison circuit;

determining whether to request more power based on the measured delay of the propagation of the clock signal through the timing comparison circuit; and

sending a voltage control signal to request more power when a determination is made to request more power based on the output of the timing comparison circuit, wherein the timing comparison circuit comprises (i) a plurality of inverters and a NOR gate, the NOR gate receiving an output from a final one of the inverters and an inverted clock signal, (ii) a register that comprises a first flip-flop generating a first status signal and a second flip-flop generating a second status signal; the register coupled to at least two delay cells, the register receiving output signals from the two delay cells; and (iii) a decoder that comprises a decoder inverter, the decoder inverter inverting the first status signal to generate a first power control signal, the decoder further providing the second status signal as a second power control signal, and wherein at least one of the first power control signal and the second power control signal are used to create the voltage control signal.