| US 7,492,659 B2 | ||
| Integrated circuit device and electronic instrument | ||
| Satoru Kodaira, Chino (Japan); Noboru Itomi, Nirasaki (Japan); Shuji Kawaguchi, Suwa (Japan); Takashi Kumagai, Chino (Japan); Hisanobu Ishiyama, Chino (Japan); and Kazuhiro Maekawa, Chino (Japan) | ||
| Assigned to Seiko Epson Corporation, Tokyo (Japan) | ||
| Filed on Nov. 10, 2005, as Appl. No. 11/270,586. | ||
| Claims priority of application No. 2005-192952 (JP), filed on Jun. 30, 2005. | ||
| Prior Publication US 2007/0013074 A1, Jan. 18, 2007 | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—226 [365/210.12; 365/189.09] | 14 Claims |
| 1. An integrated circuit device having a display memory which stores at least part of data displayed in a display panel which
has a plurality of scan lines and a plurality of data lines,
the display memory including a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells,
a plurality of first power supply interconnects for supplying a first power supply voltage to the memory cells being provided
in a metal interconnect layer in which the bitlines are formed,
a second power supply interconnect for supplying a second power supply voltage to the memory cells being provided in a metal
interconnect layer in which the wordlines are formed, the second power supply voltage being higher than the first power supply
voltage,
the bitlines being formed in a layer above the wordlines,
a plurality of bitline protection interconnects being formed in a layer above the bitlines, each of the bitline protection
interconnects at least partially covering one of the bitlines in a plan view, and
a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device
other than the display memory being provided in a layer above the bitline protection interconnects, the third power supply
voltage being higher than the second power supply voltage.
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