| US 7,492,644 B2 | ||
| Semiconductor integrated circuit device | ||
| Riichiro Takemura, Tokyo (Japan); Takeshi Sakata, Hino (Japan); Norikatsu Takaura, Tokyo (Japan); and Kazuhiko Kajigaya, Iruma (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan); and Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Aug. 02, 2007, as Appl. No. 11/832,727. | ||
| Application 11/832727 is a continuation of application No. 11/598702, filed on Nov. 14, 2006, granted, now 7,257,034. | ||
| Application 11/598702 is a continuation of application No. 10/995198, filed on Nov. 24, 2004, granted, now 7,154,788. | ||
| Claims priority of application No. P2003-398398 (JP), filed on Nov. 28, 2003. | ||
| Prior Publication US 2007/0274136 A1, Nov. 29, 2007 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—189.05 [365/205] | 7 Claims |
| 1. A semiconductor device comprising:
a bit line;
a plurality of memory cells coupled to the bit line;
a sense amplifier receiving a signal read out from one of the plurality of memory cells and a reference level, and amplifying
the signal;
a write driver coupled to the bit line and the sense amplifier, the write driver driving the bit line in order to write data
to one of the plurality of memory cells; and
an I/O line coupled to the sense amplifier via a column switch,
wherein the write driver drives the bit line according to information which is held in the sense amplifier,
wherein the write data is transferred from the I/O line to the sense amplifier via the column switch, and the amplified signal
is transferred from the sense amplifier to the I/O line via the column switch, and
wherein the column switch is selected according to an address inputted from outside the semiconductor device.
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