US 7,492,638 B2
Gated diode nonvolatile memory operation
Hsuan Ling Kao, Taipei (Taiwan); Wen Jer Tsai, Hualien (Taiwan); Tien Fan Ou, Taipei (Taiwan); and Yi Ying Liao, Sijhih (Taiwan)
Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan)
Filed on Jan. 02, 2007, as Appl. No. 11/619,125.
Claims priority of provisional application 60/866583, filed on Nov. 20, 2006.
Prior Publication US 2008/0117673 A1, May 22, 2008
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01)
U.S. Cl. 365—185.18  [365/185.05; 365/185.14] 26 Claims
OG exemplary drawing
 
1. A method of operating a nonvolatile memory device integrated circuit comprising a charge storage structure, one or more storage dielectric structures at least partly between the charge storage structure and a diode structure and at least partly between the charge storage structure and a source of gate voltage, the diode structure having a first node and a second node separated by a diffusion barrier junction, the method comprising:
applying a first bias arrangement to determine a charge storage state of the charge storage structure, wherein the first node and the second node of the diode structure are at least partly adjacent to the one or more storage dielectric structures, and the diode structure has a cross-section in which the second node has opposite sides isolated from neighboring devices by isolation dielectric; and
measuring current flowing through at least the diffusion barrier junction separating the first node and the second node of the diode structure, in reverse bias, to determine the charge storage state of the charge storage structure.