| US 7,492,569 B2 | ||
| Capacitor cell, semiconductor device and process for manufacturing the same | ||
| Taro Sakurabayashi, Kanagawa (Japan); and Toshikazu Kato, Kanagawa (Japan) | ||
| Assigned to NEC Electronics Corporation, Kanagawa (Japan) | ||
| Filed on Jun. 30, 2006, as Appl. No. 11/477,383. | ||
| Application 11/477383 is a division of application No. 10/845197, filed on May 14, 2004, granted, now 7,161,792. | ||
| Claims priority of application No. 2003-139239 (JP), filed on May 16, 2003. | ||
| Prior Publication US 2006/0249812 A1, Nov. 09, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01G 4/005 (2006.01) | ||
| U.S. Cl. 361—303 [361/302; 361/305; 361/328; 361/306.2; 361/330; 365/149; 365/230.01; 365/189.09] | 2 Claims |
| 1. A semiconductor device comprising:
a capacitor cell formed on said semiconductor substrate, including at least one capacitor element;
one interconnection layer positioned over said capacitor cell;
at least one other interconnection layer different from said one interconnection layer, on which a power supply line is provided;
at least one power supply line disposed on said one interconnection layer at an area corresponding to the area at which said
capacitor cell is placed, said power supply line being electrically connected to corresponding said power supply line on said
other interconnection layer through at least one connecting via; and
a cell disposed in the vicinity of said capacitor cell having a circuit including at least one active element;
wherein said capacitor cell constitutes a decoupling capacitor of said cell disposed in the vicinity of said capacitor cell;
wherein said power supply line provided on said one interconnection layer at an area corresponding to the area where said
capacitor cell is disposed constitutes a power supply path to said cell; and
wherein said capacitor cell is placed on one or both sides of adjacent column on which said cell is disposed on the same row
as the row on which said cell is disposed.
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