| US 7,492,341 B2 | ||
| Semiconductor circuit | ||
| Toshikazu Tachibana, Tachikawa (Japan); Yoshitaka Iwasaki, Tachikawa (Japan); Kazuya Endo, Higashimurayama (Japan); and Goro Sakamaki, Fuchu (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jul. 22, 2004, as Appl. No. 10/895,884. | ||
| Claims priority of application No. 2003-303480 (JP), filed on Aug. 27, 2003. | ||
| Prior Publication US 2005/0057549 A1, Mar. 17, 2005 | ||
| Int. Cl. G09G 5/00 (2006.01) | ||
| U.S. Cl. 345—98 [345/204] | 14 Claims |
| 1. A semiconductor circuit for supplying gate signals to a display panel in which a large number of pixels comprising active
elements are arranged in a matrix pattern, comprising:
a pre-decode circuit that receives first signals based on address signals inputted to the semiconductor circuit and that comprises:
a first decoder that decodes a first portion of the first signals and outputs first decoded signals and
a second decoder that decodes a remaining portion of the first signals and outputs second decoded signals;
level converters that convert the first decoded signals and the second decoded signals in a higher voltage level direction
and output level-converted signals;
post-decode circuits that receive the level-converted signals based on the first decoded signals and the second decoded signals
and generate the gate signals; and
gate terminals that are coupled to the post-decode circuits and output the gate signals,
wherein the number of level converters is smaller than the number of gate terminals.
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