| US 7,492,038 B2 | ||
| Semiconductor device | ||
| Yoshihiro Saeki, Tokyo (Japan); Shinji Hiratsuka, Tokyo (Japan); and Daigo Chabata, Tokyo (Japan) | ||
| Assigned to Oki Semiconductor Co., Ltd., (Japan) | ||
| Filed on Jan. 21, 2004, as Appl. No. 10/760,359. | ||
| Claims priority of application No. 2003-389483 (JP), filed on Nov. 19, 2003. | ||
| Prior Publication US 2005/0127526 A1, Jun. 16, 2005 | ||
| Int. Cl. H01L 23/02 (2006.01) | ||
| U.S. Cl. 257—686 | 22 Claims |
| 1. A semiconductor device comprising:
a first semiconductor chip;
a second semiconductor chip which is mounted on the first semiconductor chip;
a first electrode group which is located on the first semiconductor chip so as to be arranged along an outer periphery of
the second semiconductor chip;
a second electrode group which is located on the first semiconductor chip so as to be arranged along an outer periphery of
the first semiconductor chip, wherein the second electrode group surrounds the first electrode group;
a third electrode group which is located on the second semiconductor chip;
a plurality of first wires for electrically connecting the first electrode group and the third electrode group to each other;
external connection terminals which are located around the first semiconductor chip; and
a plurality of second wires for electrically connecting the second electrode group and the external connection terminals,
wherein the first semiconductor chip has a first circuit element area on which the second semiconductor chip is mounted and
a second circuit element area which is positioned between the first electrode group and the second electrode group, and wherein
the second semiconductor chip includes a memory circuit and the second circuit element area includes a logic circuit which
are susceptible to influence of noise caused outside the the logic circuit controlling the memory circuit.
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