| US 7,492,032 B2 | ||
| Fuse regions of a semiconductor memory device and methods of fabricating the same | ||
| Kwang-Kyu Bang, Hwaseong-si (Korea, Republic of); Kun-Gu Lee, Seoul (Korea, Republic of); Kyoung-Suk Lyu, Yongin-si (Korea, Republic of); Jeong-Ho Bang, Yongin-si (Korea, Republic of); Kyeong-Seon Shin, Yongin-si (Korea, Republic of); Ho-Jeong Choi, Yongin-si (Korea, Republic of); and Seung-Gyoo Choi, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Apr. 19, 2005, as Appl. No. 11/108,636. | ||
| Claims priority of application No. 10-2004-0027486 (KR), filed on Apr. 21, 2004. | ||
| Prior Publication US 2005/0236688 A1, Oct. 27, 2005 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 257—529 [257/528; 257/E23.15; 438/132; 438/333; 438/601; 438/600] | 17 Claims |
| 1. A fuse region, comprising:
an interlayer insulating layer formed on a substrate;
a fuse window defined by an inter-metal insulating layer and a passivation layer, wherein the fuse window, the inter-metal
insulating layer and the passivation layer are formed on the interlayer insulating layer,
a plurality of fuses in the fuse window; and
a plurality of inter-fuse isolation walls located between each of the plurality of fuses, each of the inter-fuse isolation
walls including lower and upper inter-fuse isolation patterns,
wherein the upper inter-fuse isolation patterns are spaced apart from the fuses to provide first gap regions between the inter-fuse
isolation walls and the fuses, and the lower inter-fuse isolation patterns are spaced apart from the fuses to provide second
gap regions between the inter-fuse isolation walls and the fuses, the space of the second gap regions being smaller than the
space of the first gap regions.
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