| US 7,492,006 B2 | ||
| Semiconductor transistors having surface insulation layers and methods of fabricating such transistors | ||
| Gyoung-Ho Buh, Gyeonggi-do (Korea, Republic of); Yu-Gyun Shin, Gyeonggi-do (Korea, Republic of); Sang-Jin Hyun, Gyeonggi-do (Korea, Republic of); and Guk-Hyon Yon, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Aug. 30, 2005, as Appl. No. 11/215,217. | ||
| Claims priority of application No. 10-2004-0068656 (KR), filed on Aug. 30, 2004; and application No. 10-2005-0047877 (KR), filed on Jun. 03, 2005. | ||
| Prior Publication US 2006/0060929 A1, Mar. 23, 2006 | ||
| Int. Cl. H01L 23/62 (2006.01) | ||
| U.S. Cl. 257—344 [257/346; 257/327; 257/410] | 32 Claims |
| 22. A semiconductor device, comprising:
a gate pattern on a substrate;
a surface insulation layer directly on at least a portion of the substrate, wherein the surface insulation layer comprises
Hf-rich hafnium oxide, Zr-rich zirconium oxide, silicon nitride and/or Al-rich aluminum oxide;
a spacer on the surface insulation layer and on a first sidewall of the gate pattern, wherein the first spacer comprises an
insulation material having a dielectric constant that is lower than a dielectric constant of the surface insulation layer;
and
a source/drain region under the first spacer;
wherein the source/drain region comprises an inversion layer in the substrate that results from surface states generated by
the surface insulation layer at the interface between the substrate and the surface insulation layer.
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