| US 7,492,002 B2 | ||
| Non-volatile memory device with a select gate electrode and a control gate electrode formed on a floating gate | ||
| Hee-Seog Jeon, Hwaseong-si (Korea, Republic of); Seung-Beom Yoon, Suwon-si (Korea, Republic of); Jeong-Uk Han, Suwon-si (Korea, Republic of); and Yong-Tae Kim, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-Si (Korea, Republic of) | ||
| Filed on Dec. 30, 2005, as Appl. No. 11/323,355. | ||
| Claims priority of application No. 10-2004-0116845 (KR), filed on Dec. 30, 2004. | ||
| Prior Publication US 2006/0170028 A1, Aug. 03, 2006 | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—321 [257/320; 257/319; 257/316] | 13 Claims |
| 1. A non-volatile memory device comprising:
a floating gate formed on a substrate with a gate insulation layer interposed therebetween;
a tunnel insulation layer formed on the floating gate;
a select gate electrode inducing charge through the gate insulation layer;
a control gate electrode inducing charge tunneling through the tunnel insulation layer and wherein at least a portion of the
select gate electrode and at least a portion of the control gate electrode are formed directly on the gate insulation layer,
wherein the select gate electrode comprising: a top select gate electrode formed over the floating gate;
and a sidewall select gate electrode formed on a sidewall of the floating gate and the gate insulation layer opposite to the
control gate electrode; and
a spacer insulation pattern interposed between the top select gate electrode and the sidewall select gate electrode and between
the top select gate electrode and the control gate electrode.
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