| US 7,492,000 B2 | ||
| Self-aligned split-gate nonvolatile memory structure and a method of making the same | ||
| Hee Seog Jeon, Hwasung (Korea, Republic of); Seung Beom Yoon, Suwon (Korea, Republic of); and Yong Tae Kim, Youngin (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jun. 01, 2006, as Appl. No. 11/444,369. | ||
| Application 11/444369 is a division of application No. 10/834082, filed on Apr. 29, 2004, granted, now 7,078,295. | ||
| Claims priority of application No. 2004-7230 (KR), filed on Feb. 04, 2004. | ||
| Prior Publication US 2006/0220105 A1, Oct. 05, 2006 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—319 [257/E21.422] | 12 Claims |
| 1. A semiconductor memory cell including a split gate cell structure comprising:
a substrate;
a common source region formed in the substrate;
a drain region formed in the substrate; the drain region being separated from the source region by a channel region;
a dielectric layer formed on the channel region;
a floating gate electrode arranged on the dielectric layer above a first portion of the channel region adjacent the source
region;
a control gate electrode arranged on the dielectric layer above a second portion of the channel region adjacent the drain
region, the floating gate and control gate electrodes being operable to control the channel region;
wherein a projecting portion of the control gate electrode extends over an adjacent portion of the floating gate electrode,
the projecting portion including an upper portion and a lower portion, located below the upper portion in a vertical direction,
and the upper portion having a substantially vertical surface and extending a first distance over the floating gate electrode,
the lower portion having a substantially non-vertical surface and extending a second distance over the floating gate electrode,
the first distance being less than the second distance, and
wherein the upper portion does not extend over the lower portion.
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