	US 7,491,999 B2
	Non-volatile memory cells utilizing substrate trenches
Eliyahou Harari, Saratoga, Calif. (US); Jack H. Yuan, Cupertino, Calif. (US); George Samachisa, San Jose, Calif. (US); and Henry Chien, San Jose, Calif. (US)
Assigned to Sandisk Corporation, Milpitas, Calif. (US)
Filed on Jun. 08, 2006, as Appl. No. 11/423,121.
Application 10/848242 is a division of application No. 09/925134, filed on Aug. 08, 2001, granted, now 6,936,887.
Application 11/423121 is a continuation of application No. 10/848242, filed on May 17, 2004, granted, now 7,087,951.
Application 09/925134 is a continuation in part of application No. 09/860704, filed on May 18, 2001, granted, now 6,894,343.
Prior Publication US 2006/0227620 A1, Oct. 12, 2006
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/72 (2006.01)

U.S. Cl. 257—315 [257/314; 257/319; 438/270; 438/524; 438/525]

13 Claims

1. A process of fabricating a non-volatile memory cell array, comprising:

forming strips of electrically conductive material across a semiconductor substrate with a layer of dielectric therebetween, the conductive material strips being elongated in a first direction across the substrate and being spaced apart in a second direction, wherein the first and second directions are orthogonal with each other,

etching trenches into the substrate between at least every other one of the conductive strips, said trenches being defined by positions of the conductive strips and having lengths extending in the first direction,

thereafter implanting ions along the lengths of the trenches to form elongated sources and drains in said trenches,

thereafter separating the strips of conductive material into individual floating gates, thereby forming a two-dimensional array of floating gates,

forming a first plurality of elongated gates extending across the array of floating gates in the first direction that extend into the trenches crossed by them, and

forming a second plurality of elongated gates.