	US 7,491,973 B2
	Semiconductor LSI circuit having a NAND logic gate with a highly integrated and microscopic structure
Kazuya Matsuzawa, Kawasaki (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Jun. 24, 2005, as Appl. No. 11/165,194.
Claims priority of application No. P2005-057388 (JP), filed on Mar. 02, 2005.
Prior Publication US 2006/0197111 A1, Sep. 07, 2006
Int. Cl. H01L 29/10 (2006.01); H01L 29/73 (2006.01); H01L 29/76 (2006.01)

U.S. Cl. 257—67 [257/206; 257/365; 257/369]

12 Claims

1. A semiconductor LSI circuit, comprising:

a first semiconductor region;

a first gate insulating layer on one side of the first semiconductor region;

a first gate electrode of a first conductivity type on the first gate insulating layer;

a first source region and a common drain region sandwiching the first semiconductor region;

a second gate insulating layer on the other side of the first semiconductor region;

a second gate electrode of a second conductivity type opposite to the first conductivity type on the second gate insulating layer;

a second semiconductor region adjacent to the common drain region;

a third gate insulating layer on one side of the second semiconductor region;

a third gate electrode on the third gate insulating layer;

a second source region adjacent to the second semiconductor region and the common drain region;

a fourth gate insulating layer on the other side of the second semiconductor region; and

a fourth gate electrode on the fourth gate insulating layer;

wherein the first semiconductor region, the first gate insulating layer, the first gate electrode, the first source region, and the common drain region constitute a first transistor; the first semiconductor region, the second gate insulating layer, the second gate electrode, the first source region, and the common drain region constitute a second transistor; the second semiconductor region, the third gate insulating layer, the third gate electrode, the second source region, and the common drain region constitute a third transistor; and the second semiconductor region, the fourth gate insulating layer, the fourth gate electrode, the second source region, and the common drain region constitute a fourth transistor, and

wherein the electron affinity of the second pate electrode is smaller than that of the first pate electrode, and the first throuph the fourth transistors constitute a NAND pate.