| US 7,491,971 B2 | ||
| Transistor array panel, liquid crystal display panel, and method of manufacturing liquid crystal display panel | ||
| Yayoi Nakamura, Hino (Japan) | ||
| Assigned to Casio Computer Co., Ltd., Tokyo (Japan) | ||
| Filed on Jul. 24, 2006, as Appl. No. 11/492,114. | ||
| Claims priority of application No. 2005-215717 (JP), filed on Jul. 26, 2005. | ||
| Prior Publication US 2007/0023752 A1, Feb. 01, 2007 | ||
| Int. Cl. H01L 29/04 (2006.01) | ||
| U.S. Cl. 257—59 [257/72; 257/40; 257/E27.1; 257/E29.117] | 5 Claims |
| 1. A liquid crystal display panel comprising:
(a) a transistor array panel including:
one substrate;
a plurality of gate lines and a plurality of data lines arranged on one side of said one substrate to cross one another;
an insulating film interposed between the plurality of gate lines and the plurality of data lines;
a plurality of first thin-film transistors provided in intersecting portions between the plurality of gate lines and the plurality
of data lines on the one side of said one substrate, respectively;
a plurality of pixel electrodes connected to the first thin-film transistors, respectively;
a gate electrode of each first thin-film transistor being connected to one of the plurality of gate lines;
one of a drain electrode and a source electrode of each first thin-film transistor being connected to one of the plurality
of pixel electrodes;
the other of the drain electrode and the source electrode which is not connected to the pixel electrode being connected to
one of the plurality of data lines;
at least one conductive film pattern formed to be electrically insulated from the plurality of gate lines, the plurality of
data lines and the plurality of pixel electrodes, and to be overlapped on the pixel electrodes, thereby forming a storage
capacitance between each of the pixel electrodes and the conductive film pattern;
a protection circuit electrically connected to the gate lines and the data lines, and disposed in a plane direction of said
one substrate in an outer peripheral portion of a display region in which the plurality of first thin-film transistors and
the plurality of pixel electrodes are formed on the one side of said one substrate; and
a first common line which is: (i) insulated from the protection circuit in the outer peripheral portion of the display region,
(ii) electrically connected to the at least one conductive film pattern, (iii) arranged to be at least partially overlapped
on the protection circuit, and (iv) disposed nearer to said one substrate than the pixel electrodes are;
(b) a counter substrate assembly including:
another substrate; and
an electrode formed on one side of said another substrate; and
(c) a liquid crystal hermetically introduced between the transistor array panel and the counter substrate assembly arranged
to face each other.
|