| US 7,491,970 B2 | ||
| IC with comparator receiving expected and mask data from pads | ||
| Lee D. Whetsel, Parker, Tex. (US); and Alan Hales, Richardson, Tex. (US) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Jan. 09, 2008, as Appl. No. 11/971,561. | ||
| Application 11/626201 is a division of application No. 11/103781, filed on Apr. 11, 2005, granted, now 7,183,570, filed on Feb. 27, 2007. | ||
| Application 11/103781 is a division of application No. 10/301898, filed on Nov. 22, 2002, granted, now 6,894,308, filed on May 17, 2005. | ||
| Application 11/971561 is a continuation of application No. 11/626201, filed on Jan. 23, 2007, abandoned. | ||
| Claims priority of provisional application 60/333803, filed on Nov. 28, 2001. | ||
| Prior Publication US 2008/0106287 A1, May 08, 2008 | ||
| Int. Cl. H01L 23/58 (2006.01); G01R 31/26 (2006.01) | ||
| U.S. Cl. 257—48 [438/18; 324/765] | 6 Claims |
| 1. An integrated circuit comprising:
A. first and second die pads;
B. core circuitry having core input leads and core output leads;
C. a first buffer having an input lead connected to a first core output lead, a tri-state enable lead, and an output lead
connected to the first die pad;
D. a second buffer having an input lead and an output lead connected between the second die pad and one of a core input lead
and a second core output lead; and
E. comparator circuitry having a core input lead connected to the first core output lead, a test enable lead connected to
the tri-state enable lead, an expected data input lead connected to one of the first die pad and the second die pad, and a
mask data input lead connected to the other of the first die pad and the second die pad.
|