| US 7,491,963 B2 | ||
| Non-volatile memory structure | ||
| Terry L. Gilton, Boise, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Aug. 23, 2007, as Appl. No. 11/844,079. | ||
| Application 11/844079 is a continuation of application No. 11/143729, filed on Jun. 03, 2005, granted, now 7,276,722. | ||
| Application 11/143729 is a continuation of application No. 10/663741, filed on Sep. 17, 2003, granted, now 6,903,361. | ||
| Prior Publication US 2007/0297231 A1, Dec. 27, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 47/00 (2006.01) | ||
| U.S. Cl. 257—2 [257/5] | 17 Claims |
| 1. A memory cell, comprising:
a substrate, the substrate including a source region and a drain region;
a first insulating material over the substrate;
a first conductive material and a second conductive material over the first insulating material and between the source and
drain regions;
a programmable resistance element formed between the first and second conductive materials, the programmable resistance element
having a resistance which is controllable between at least two states.
|