| US 7,491,896 B2 | ||
| Information handling system utilizing circuitized substrate with split conductive layer | ||
| John M. Lauffer, Waverly, N.Y. (US); James M. Larnerd, Binghamton, N.Y. (US); and Voya R. Markovich, Endwell, N.Y. (US) | ||
| Assigned to Endicott Interconnect Technologies, Inc., Endicott, N.Y. (US) | ||
| Filed on Jan. 18, 2008, as Appl. No. 12/10,004. | ||
| Application 12/010004 is a division of application No. 11/641810, filed on Dec. 20, 2006, granted, now 7,377,033. | ||
| Application 11/641810 is a division of application No. 10/882167, filed on Jul. 02, 2004, granted, now 7,157,646. | ||
| Prior Publication US 2008/0117583 A1, May 22, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H05K 1/11 (2006.01) | ||
| U.S. Cl. 174—262 [174/255; 174/263; 174/264; 174/265; 174/266; 361/761; 361/763; 257/698] | 4 Claims |
| 1. An information handling system comprising:
a housing;
an electrical assembly positioned substantially within said housing and including a circuitized substrate having at least
one electrically conductive layer of substantially planar configuration and having first and second opposing surfaces, said
at least one electrically conductive layer including at least two separate, electrically isolated portions, each electrically
isolated portion including an edge portion substantially facing an edge portion of at least one other electrically isolated
portion, each of said edge portions facing each other comprised of a plurality of contiguous formed open segments, a first
dielectric layer positioned on said first opposing surface of said at least one electrically conductive layer, a portion of
said first dielectric layer being positioned within selected ones of said contiguous formed open segments of each of said
facing edge portions, said first dielectric layer including a plurality of openings each aligned above a respective one of
the remaining ones of said contiguous formed open segments, and a second dielectric layer positioned on said second opposing
surface of said at least one electrically conductive layer, a portion of said second dielectric layer being positioned within
said remaining ones of said contiguous formed open segments of each of said facing edge portions and within said plurality
of openings within said first dielectric layer aligned above said respective ones of said remaining ones of said contiguous
formed open segments, only said portion of said first dielectric layer being positioned within said selected ones of said
contiguous formed open segments of each of said facing edge portions and substantially only said portion of said second dielectric
layer being positioned with said remaining ones of said contiguous formed open segments of each of said facing edge portions
and within said plurality of openings within said first dielectric layer aligned above said respective ones of said remaining
ones of said contiguous formed open segments, said portions of both of said first and second dielectric layers positioned
within said contiguous formed open segments of said facing edge portions providing a common, substantially solid dielectric
barrier between said facing edge portions; and
at least one electrical component positioned on and electrically coupled to said circuitized substrate of said electrical
assembly.
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