| US 7,491,642 B2 | ||
| Electrical passivation of silicon-containing surfaces using organic layers | ||
| Nathan S. Lewis, La Canada, Calif. (US); and William Royea, Chicago, Ill. (US) | ||
| Assigned to The California Institute of Technology, Pasadena, Calif. (US) | ||
| Filed on Jul. 12, 2001, as Appl. No. 9/905,157. | ||
| Claims priority of provisional application 60/217749, filed on Jul. 12, 2000. | ||
| Prior Publication US 2002/0139975 A1, Oct. 03, 2002 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—642 [438/643] | 15 Claims |
| 1. A process for forming a semiconductor substrate, comprising:
providing a monocrystalline silicon-containing material having a porosity of not more than 30%, H-terminated and having a
surface substantially free of oxidation; and
forming an organic layer having more than half of its atoms being carbon and hydrogen in the presence of an alcohol-ferrocene
solution, wherein the organic layer is chemically bonded to the surface of the silicon-containing material, wherein an electrical
property selected from surface recombination velocity, carrier lifetime, electronic efficiency, voltage, device capacitance,
contact resistance, and resistance of a doped region of the semiconductor substrate is changed at compared to the electrical
property of the substrate in the absence of the organic layer, thereby forming a semiconductor substrate, and
wherein as a result of said organic layer being chemically bonded to the surface of the silicon-containing material, said
surface comprises a measurable carrier lifetime for low-level injection of more than approximately 7.8 μs or for high-level
injection of more than approximately 12 μs, or a measurable surface recombination velocity of less than approximately 1300
cm/s for low-level injection or 810 cm/s for high-level injection.
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