| US 7,491,622 B2 | ||
| Process of forming an electronic device including a layer formed using an inductively coupled plasma | ||
| Michael D. Turner, San Antonio, Tex. (US); Mohamad M. Jahanbani, Austin, Tex. (US); Toni D. Van Gompel, Austin, Tex. (US); and Mark D. Hall, Austin, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Apr. 24, 2006, as Appl. No. 11/409,790. | ||
| Prior Publication US 2007/0249160 A1, Oct. 25, 2007 | ||
| Int. Cl. H01L 21/76 (2006.01); H01L 23/58 (2006.01) | ||
| U.S. Cl. 438—438 [257/647] | 19 Claims |
| 1. A process of forming an electronic device comprising:
patterning a semiconductor layer to define an opening extending to an insulating layer,
wherein the insulating layer lies between a substrate and the semiconductor layer,
wherein after patterning the semiconductor layer:
the semiconductor layer has a sidewall and a surface;
the surface is spaced apart from the insulating layer; and
the sidewall extends from the surface towards the insulating layer; and chemical vapor depositing a first layer adjacent to
the sidewall, wherein:
the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface; and
chemical vapor depositing the first layer is performed:
using an inductively coupled plasma;
at a pressure no greater than approximately 20 mTorr;
using a chamber that is coupled to a biasing power supply and an ionizing power supply; and
during chemical vapor depositing, the biasing power supply provides a first power to the chamber at a first power flux no
greater than approximately 1.6 watts/cm2, and the ionizing power supply provides a second power to the chamber at a second power flux that is more than double the
first power flux.
|