| US 7,491,617 B2 | ||
| Transistor structure with minimized parasitics and method of fabricating the same | ||
| David R. Greenberg, White Plains, N.Y. (US); and Shwu-Jen Jeng, Wappingers Falls, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 18, 2007, as Appl. No. 11/764,388. | ||
| Application 11/764388 is a division of application No. 11/481070, filed on Jul. 05, 2006, granted, now 7,253,070. | ||
| Application 11/481070 is a division of application No. 10/789282, filed on Feb. 27, 2004, granted, now 7,075,126, filed on Jul. 11, 2006. | ||
| Prior Publication US 2007/0241428 A1, Oct. 18, 2007 | ||
| Int. Cl. H01L 21/331 (2006.01) | ||
| U.S. Cl. 438—345 [438/366; 257/E21.371; 257/E21.379] | 4 Claims |
| 1. A method of forming a bipolar transistor comprising the steps of:
forming a first conductivity first epitaxially grown silicon-containing layer atop second conductivity portion of a substrate;
forming at least two isolation regions in said first conductivity epitaxially grown silicon-containing layer, wherein an active
area is formed between said at least two isolation regions;
forming a base window dielectric layer atop said first conductivity epitaxially grown silicon-containing layer and said at
least two isolation regions; wherein said base window dielectric layer is removed within said active area;
forming first conductivity second epitaxial extrinsic base regions, each first conductivity epitaxial base region of said
first conductivity extrinsic base regions separated by an emitter channel, said emitter channel exposing a portion of said
first conductivity epitaxially grown silicon-containing layer; and
forming a second conductivity emitter within said emitter channel, wherein said emitter is separated from said first conductivity
extrinsic base regions by emitter/base spacers.
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