US 7,491,568 B2
Wafer level package and method for making the same
Wei-Chung Wang, Kaoshiung (Taiwan)
Assigned to Advanced Semiconductor Engineering, Inc., Kaoshiung (Taiwan)
Filed on Dec. 22, 2005, as Appl. No. 11/314,341.
Claims priority of application No. 94128942 A (TW), filed on Aug. 24, 2005.
Prior Publication US 2007/0048899 A1, Mar. 01, 2007
Int. Cl. H01L 21/00 (2006.01)
U.S. Cl. 438—51 8 Claims
OG exemplary drawing
 
1. A wafer level packaging method comprising the steps of:
(a) providing a metal layer, the metal layer having a first surface and a second surface;
(b) forming a plurality of first caves and a plurality of second caves on the first surface;
(c) forming a cover in each first cave and around each first cave, and forming a conductive portion in each second cave and around each second cave;
(d) disposing a wafer onto the covers and the conductive portions; and
(e) removing the metal layer.