| US 7,490,309 B1 | ||
| Method and system for automatically optimizing physical implementation of an electronic circuit responsive to simulation analysis | ||
| Taranjit Singh Kukal, Delhi (India); and Alok Tripathi, Noida (India) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Aug. 31, 2006, as Appl. No. 11/513,061. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—10 [716/12; 716/13; 716/14; 716/15] | 24 Claims |
| 1. A method of optimizing physical implementation of an electronic circuit responsive to simulation analysis thereof, comprising:
a. schematically defining the electronic circuit to include a plurality of circuit elements interconnected at respective nodes
by a plurality of nets;
b. acquiring parametric values for a plurality of predetermined operational parameters from simulated operation of the electronic
circuit;
c. automatically processing said parametric values to generate a plurality of parametric constraints corresponding thereto
for optimizing physical implementation of the electronic circuit, said processing selectively translating said parametric
values to said parametric constraints in accordance with at least one predefined mapping rule; and,
d. generating a circuit layout at least partially representing a physical implementation of said schematic definition, said
circuit layout including a plurality of devices interconnected by a plurality of tracks, said circuit layout being adaptively
configured in accordance with said parametric constraints.
|