	US 7,490,260 B2
	Method and apparatus for reconfigurable memory
Siva Venkatraman, San Jose, Calif. (US); Earle F. Philhower, III, Union City, Calif. (US); Ruban Kanapathippillai, Dublin, Calif. (US); and Manoj Mehta, Laguna Hill, Calif. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Sep. 01, 2005, as Appl. No. 11/219,008.
Application 11/219008 is a continuation of application No. 10/056393, filed on Jan. 24, 2002, granted, now 7,111,190.
Claims priority of provisional application 60/271139, filed on Feb. 23, 2001.
Prior Publication US 2006/0010335 A1, Jan. 12, 2006
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01)

U.S. Cl. 714—7 [714/5]

9 Claims

1. A method comprising:

testing a memory in an integrated circuit to determine a location of one or more bad memory cells;

determining a total memory capacity of the integrated circuit, wherein the total memory capacity does not include the one or more bad memory cells;

binning out the total memory capacity of the integrated circuit;

organizing the memory into one or more clusters, each of the one or more clusters having one or more memory blocks;

locating one or more bad memory cells within one or more respective memory blocks; and

mapping out, by a reconfigurable memory controller, the one or more respective memory blocks having the one or more bad memory cells,

wherein the reconfigurable memory controller to map out one or more physical addresses of memory blocks having the one or more bad memory cells,

wherein the reconfigurable memory controller to includes a configuration register associated with each memory block, each configuration register including a memory block enable bit, the memory block enable bit to map out the respective memory blocks having the bad memory cells, and

wherein each configuration register further to include a base address associated with one or more upper address bits of an address to begin the physical addressing of a respective memory block having all good memory cells.