a plurality of register files, each register file comprising a random access memory (RAM) comprising a single port for read operations and for write operations, wherein for at least one of a plurality of data groups each RAM serially performs N read operations and M write operations in a single clock cycle of a single assigned clock phase of (N+M) clock phases generated from a clock, wherein each of said (N+M) clock phases is shifted from each other by at least one clock cycle of said clock, and wherein said clock cycle of each assigned clock phase includes (N+M) clock cycles of said clock;

an input staging unit for staging write data of one or more of said write operations, wherein said input staging unit is coupled to said plurality of register files and comprises a configuration dependent on value of M; and

an output staging unit for staging read data of one or more of said read operations, wherein said output staging unit is coupled to said plurality of register files and comprises a configuration dependent on value of N.