first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other;

a synchroniser operable to synchronise a signal processed by said first logic to produce a signal synchronised to said second clock domain;

a synchronised signal output operable to export from said data processor said synchronised signal processed by said first logic; and

a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein

said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises:

combining logic arranged to receive said exported synchronised signals from each of said plurality of data processors and to combine said exported synchronised signals to produce a resultant signal, said resultant signal being routed to each of said signal inputs of said plurality of data processors.