| US 7,489,588 B2 | ||
| Semiconductor memory device having a main amplifier equipped with a current control circuit in a burst read operation | ||
| Satoru Hanzawa, Hachioji (Japan); Tomonori Sekiguchi, Tama (Japan); Riichiro Takemura, Tokyo (Japan); Satoru Akiyama, Kawasaki (Japan); and Kazuhiko Kajigaya, Iruma (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan); and Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Oct. 25, 2007, as Appl. No. 11/924,353. | ||
| Application 11/924353 is a continuation of application No. 11/467793, filed on Aug. 28, 2006, granted, now 7,304,910. | ||
| Claims priority of application No. 2005-378490 (JP), filed on Dec. 28, 2005. | ||
| Prior Publication US 2008/0094922 A1, Apr. 24, 2008 | ||
| Int. Cl. G11C 7/08 (2006.01) | ||
| U.S. Cl. 365—233.18 [365/233.13; 365/196; 365/190; 365/208; 365/207; 365/227] | 8 Claims |
| 1. A semiconductor device comprising:
a plurality of memory cells;
a first signal line pair to transfer information stored in one of the plurality of memory cells; and
a main amplifier connected to the first signal line pair and including a static type differential amplifier, the static type
differential amplifier including a first transistor whose gate is connected to one line of the first signal line pair, a second
transistor whose gate is connected to the other line of the first signal line pair, and a current control circuit connected
between a first potential and sources of the first and second transistors,
wherein the current control circuit generates a first current in a first cycle of a burst read operation and a second current
smaller than the first current in a second cycle of the burst read operation after the first cycle of the burst read operation.
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